Maxim Integrated Secure Microcontroller - Manual (Page 46)

Secure Microcontroller User’s Guide
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DS5001/DS5002 RPC Control Register
RPCTL, 0D8H
D7 D6 D5 D4 D3 D2 D1 D0
RNR — EXBS AE IBI DMA RPCON RG0
R-0 RW-0 RT-0 R*W*-0 RW*-0 RW-0 RB-*
R = Unrestricted Read Access, W = Unrestricted Write Access, T = Timed-access Write Only, B = Modifiable only via Bootstrap Loader, n =
Value after Reset, * = Special: see description
RPCTL.7 RNR
When internal hardware sets this read-only bit to 1, a new random number is
available from the random number generator register of the DS5001/DS5002
(RNR;0CFh). This bit is cleared when the random number is read, and
approximately 160ms are required to generated the next number. Because a reset
initiates the generation of a new random number, this bit will be set approximately
160
µs after a reset.
RPCTL.5
EXBS
When this bit is set, all data memory (MOVX) accesses are routed to the expanded
bus (Ports 0 and 2). When cleared, MOVX accesses are touted to the bytewide
bus. This bit cannot be modified via the bootstrap loader.
RPCTL.4
AE
Access enable is used when a software reload is desired without using the
bootstrap loader. When set, the device is temporarily configured in a partitionable
configuration with the partition at 4kB. This occurs even if PM = 1. When cleared,
the prior memory configuration is resumed. This bit cannot be modified via the
bootstrap loader.
RPCTL.3
IBI
When this bit is set, the timer 1 interrupt is disabled and the interrupt vector (1Bh)
is converted to function as the RPC mode interrupt. This bit can be set only when
the RPCON bit is set. This bit is cleared on all resets and when the RPCON bit is
cleared. This bit cannot be modified via the bootstrap loader.
RPCTL.2
DMA
This bit is set to enable DMA transfers when RPC mode is invoked. It can only be
set when RPCON = 1. This bit is cleared on all resets and when the RPC is
cleared. This bit cannot be modified via the bootstrap loader.
RPCTL.1
RPCON
Enable the RPC 8042 I/O protocol. When set, port 0 becomes the data bus, and
port 2 becomes the control signals. This bit cannot be modified via the bootstrap
loader.
RPCTL.0
RG0
This is one of two range bits that determine the size of the program memory space.
Its usage is shown above. It is cleared on a no-V
LI
reset or clearing of the security
lock and unaffected by any other reset.