Table 14-c. serial i/o operating modes – Maxim Integrated Secure Microcontroller User Manual

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Table 14-C. Serial I/O Operating Modes

MODE

SYNC/ASYNC

BAUD CLOCK

DATA BITS

START/STOP

9TH DATA BIT

FUNCTION

MODE 0

SYNC

12 t

CLK

8

None

None

MODE 1

ASYNC

Timer 1

8

1 Start

None

Overflow

1 Stop

MODE 2

ASYNC

32 t

CLK

or

9

1 Start

0, 1, or parity

64 t

CLK

1 Stop

MODE 3

ASYNC

Timer 1

9

1 Start

0, 1, or parity

Overflow

1 Stop


The serial port is controlled by the SCON register. Serial interrupts are also used, which are controlled by
IE and IP. The setup for each SFR is shown below. In addition, Mode 1 is associated with Timer 1, which
is controlled by TCON and TMOD.

Mode 1 is selected using the SCON register. The table from the SCON register shown below indicates
that Mode 1 is selected by choosing the value SM0 = 0 and SM1 = 1.

SM0

SM1

MODE

FUNCTION

WORD LENGTH

BAUD CLOCK

0

0

Mode 0

Synchronous

8 bits

12 t

CLK

0

1

Mode 1

Asynchronous

10 bits

Timer 1 Overflow

1

0

Mode 2

Asynchronous

11 bits

32 t

CLK

or 64 t

CLK

1

1

Mode 3

Asynchronous

11 bits

Timer 1 Overflow


SM0 = 0 and SM1 = 1 corresponds to the value SCON.7 = 0 and SCON.6 = 1. In addition, since the
application must receive data, the serial receiver must be enabled. This is done by setting the REN bit at
SCON.4 to a logic 1. The remaining bits in SCON can be written to 0. Thus the value for SCON is 50h.

SCON–98h

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

0

1

0

1

0

0

0

0

This application uses the serial interrupt, which serves two purposes. First, the software knows when a
byte has been sent, so it knows when another can be written. Second, after the 256 bytes have been
transmitted, the PC will respond. It is not known when this occurs, and the software may have other tasks
to attend. Therefore, the serial interrupt will inform the microcontroller when the confirmation code has
been received by the serial port. This example enables only the serial interrupt. It is set for high priority
since other interrupts might be enabled in a real system.

IE–0A8h

EA

ES

ET1

EX1

ET0

EX0

1

0

0

1

0

0

0

0

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