Moog Crossbow GNAV540 - Manual (Page 36)

Page 36
GNAV540 User Manual
7430‐0808‐01 Rev. B
I/O Port Interface
The following ports are accessible through the J1 connector. Refer to J1—I/O Connector on page 35 for the pin out
listing.
NOTE: The GNAV540 can be purchased with a developer’s kit: a cable is provided with a 37 pin connector on one
end, and five connectors on the other end to connect to external devices. This cable is designed only for
laboratory use. See Figure 31 on page 126.
Port A: User (computer), RS422 serial data interface
This serial interface is standard RS‐422, 9600, 19200, 38400, or 57600 baud, 8 data bits, 1 start bit, 1 stop bit, no
parity, and no flow control and will output at a user configurable output rate. These settings allow interaction via a
standard PC serial port
Port B: External GPS, RS422 serial interface
This serial interface is standard RS‐422, which connects to the external GPS. GNAV540 supports a GPS‐ICD‐153C
compliant GPS receiver.
Port C: External Magnetometer, RS422 serial interface
This serial interface is standard RS‐422. The settings for an external magnetometer are 38400 baud, 8 data bit,
1 start bid, 1 stop bit, no parity, no flow control.
Cable Field Requirements
CAUTION: The GNAV540 is shipped with an EMI filter attached to the Amphenol (MIL‐DTL‐38999‐III), TVP02R
Receptacle, 37 pins circular connector. This connector must remain in place to ensure proper shielding from
EMI interference. The cable sent with the unit is intended to provide the user with the ability to test the unit
right out of the box, and will not provide adequate shielding for all environments.
For field use, the cable must be used with the shield connected to the I/O connector shell to provide the required
EMI protection. Case ground must be used to provide full EMI protection; Ensure the cable shield is grounded on
only one end of the cable.
Signals
Hardware BIT Error Output
The hardware BIT error output pin is the ultimate indication of system failure. This indication is available in most
software output packets as the masterFail flag. It is the logical AND of the hardwareError, comError, and
softwareError flags monitored by the system. In the event of a communication failure, the hardware BIT error pin
may be used to detect a masterFail assertion. This pin is open‐collector and requires a 1k to 10k ohm pull‐up
resister. The system will drive this pin low to assert a system failure.
1 PPS Input Interface
The 1PPS input signal allows the user of the GNAV540 to force synchronization of sensor data collection to a 1Hz
rising‐edge signal. The signal must maintain 0.0‐0.2 V zero logic and 3.0‐5.0 volts high logic and stay within 100ms
of the internal system 1 second timing. Sending this signal to the system will align the sensor data collection and
algorithm processing to its rising edge and 10ms boundaries thereafter. When the system is synchronized to 1PPS,
the hardwareStatusÆunlocked1PPS flag will be zero; otherwise, the flag will be one.