Pci-e interface, Reset and interrupts, Figure 7-2 switch reset requirements – ADLINK aTCA-N700 User Manual
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aTCA-N700 HW Users Guide
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7.3. PCI-e Interface
Trident supports a 2-lane, PCI-Express (PCIe) Generation 2 interface for CPU
configuration and control plane access. A single clock source of 100MHz differential for
the PCIe is required and provided on the board to the PCIE_REFCLKp/n pin. The
interface supports different types of the DMA operations:
• Scatter-gather DMA for packet transfer to CPU.
• Table DMA: For copying any switch table into system memory
• Statistics DMA: For gathering on-chip statistics counters
• Packet DMA: For transferring packets from/to the CPU
7.4. Reset and Interrupts
Figure 7-2 illustrates the Reset requirements of the switch, which is copied from the
datasheet.
On the board, the Reset pin is driven by the CPLD which generates a compliant reset
signal for the switch.
Figure 7-2 Switch Reset Requirements