Altera Remote Update IP Core - Manual (Page 11)

Components Details
Remote configuration
registers
The remote configuration registers keep track of page addresses and the cause
of configuration errors. You can control both the update and shift registers.
The status and control registers are controlled by internal logic, but are read
via the shift register. The control register is 38-bit wide.
For details about configuration registers, refer to the Configuration, Design
Security, and Remote System Upgrades chapter in the respective device
handbook.
Parameter Settings
Table 3: Altera Remote Update IP Core Parameters for Arria 10 Devices
GUI Name Legal Value in GUI Description
Which operation mode
will you be using?
REMOTE Specifies the configuration mode of the ALTERA
REMOTE UPDATE IP core.
Which configuration
device will you be using?
EPCQ-L device Choose the configuration device you are using.
Add support for writing
configuration parameters
—
Enable this if you need to write configuration
parameters.
Enable reconfig POF
checking
—
Not available as it is not required
Ports
Table 4: Altera Remote Update IP Core Ports for Arria 10 Devices
Name Port Required? Description
read_param
Input
No Read signal for the parameter specified in
param[]
input port and fed to
data_out[]
output port.
Signal indicating the parameter specified on the
param[]
port should be read. The number of bits set
on
data_out[]
depends on the parameter type. The
signal is sampled at the rising clock edge. Assert the
signal for only one clock cycle to prevent the
parameter from being read again in a subsequent
clock cycle.
The busy signal is activated as soon as
read_param
is
read as active. While the parameter is being read, the
busy signal remains asserted, and
data_out[]
has
invalid data. When the busy signal is deactivated,
data_out[]
is valid, another parameter can be read.
UG-31005
2015.04.07
Parameter Settings 11
Altera Remote Update IP Core User Guide Altera Corporation
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