Altera FIR Compiler - Manual (Page 18)

2–4 Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
FIR Compiler User Guide © May 2011 Altera Corporation
2. Click Step 2: Setup Simulation in IP Toolbench to display the Set Up Simulation -
FIR Compiler page ( Figure 2–4 ).
3. Turn on Generate Simulation Model to create an IP functional model.
1
An IP functional simulation model is a cycle-accurate VHDL or Verilog
HDL model produced by the Quartus II software.
Figure 2–3. IP Toolbench—Parameterize
Figure 2–4. Set Up Simulation