Altera FIR Compiler - Manual (Page 59)

Chapter 4: Functional Description 4–17
Timing Diagrams
© May 2011 Altera Corporation FIR Compiler User Guide
Timing Diagrams
The reset_n signal resets the control logic and state machines that control the FIR
Compiler (not including data storage elements that hold previous inputs used to
calculate the result).
The previous data is not cleared when the reset_n signal is applied. To clear the
data, set the ast_sink_data port to 0 for n clock cycles, where n = (number of
coefficients) × (number of input channels) × (number of clock cycles needed to compute a FIR
result).
The FIR output value depends on the coefficient values in the design. Therefore, the
timing diagrams of your own design may be different than those shown in the
following figures. However, you can use the testbench generated by the FIR compiler
to get the correct timing relation between signals for a specific parameterized case.
All timing diagrams assume a full streaming operation where ast_source_ready
and ast_sink_ready are always 1 (unless otherwise stated).
ast_source_channel Output Indicates the index of the channel whose result is presented at the data output.
The width of this signal = log
2
(number of channels).
ast_source_data Output Filter output. The data width depends on the parameter settings.
ast_source_sop Output Marks the start of the outgoing FIR filter result group. If '1', a result
corresponding to channel 0 is output.
ast_source_eop Output Marks the end of the outgoing FIR filter result group. If '1', a result corresponding
to channel N-1 is output, where N is the number of channels.
ast_source_error Output Error signal indicating Avalon-ST protocol violations on the source side:
■ 00: No error
■ 01: Missing SOP
■ 10: Missing EOP
■ 11: Unexpected EOP
Other types of errors are also marked as 11.
coef_set Input Selects which coefficient set the FIR filter uses for the calculation. (Appears when
multiple coefficient sets are used.) The width of this signal = log
2
(number of
coefficient sets).
coef_in_clk Input Clock to reload coefficients when coefficients are stored in memory. (Appears
when the Coefficient Reload option is selected and the Use Single Clock option is
not selected) This clock can be different than
clk .
coef_set_in Input Selects which coefficient set to be reloaded. (Appears when multiple coefficient
sets are used and the Coefficient Reload option is selected.) The width of this
signal = log
2
(number of coefficient sets)
coef_in Input Input coefficient value when reloading coefficient. (Appears when the Coefficient
Reload option is selected)
coef_we Input Active high write enable signal. Enables coefficient overwriting when coefficients
are reloadable.
coef_ld Output Coefficient reload control port. This port is created only when multicycle filters are
selected and the coefficient storage is logic cells.
Table 4–3. FIR Compiler Signals (Part 2 of 2)