Altera FIR Compiler - Manual (Page 39)

Chapter 3: Parameter Settings 3–15
Specify the Architecture Specification
© May 2011 Altera Corporation FIR Compiler User Guide
1. For this tutorial, select Distributed Arithmetic: Fully Parallel Filter structure with
a pipeline level of 3.
Although these settings create a filter that uses a large number of logic cells,
increasing the pipeline level to 3 decreases the number of clock cycles to one,
thereby greatly increasing system performance. These settings are shown in
Figure 3–9 .
2. Click Finish when you have set the architecture parameters.
Figure 3–9. Specify the Filter Architecture