Altera FIR Compiler - Manual (Page 20)

2–6 Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
FIR Compiler User Guide © May 2011 Altera Corporation
Generate the MegaCore Function
To generate your MegaCore function variation, perform the following steps:
1. Click Step 3: Generate in IP Toolbench to generate your MegaCore function
variation and supporting files. The generation phase may take several minutes to
complete. The generation progress and status is displayed in a report window.
Figure 2–6 shows the generation report.
Table 2–1 describes the IP Toolbench-generated files and other files that may be in
your project directory. The names and types of files specified in the report vary
based on whether you created your design with VHDL or Verilog HDL.
Figure 2–6. Generation Report - FIR Compiler MegaCore Function
Table 2–1. Generated Files (Part 1 of 2) (Note 1) , (2)
Filename Description
<entity name>.vhd A VHDL wrapper file for the Avalon-ST interface.
<variation name>.bsf A Quartus II block symbol file for the MegaCore function variation. You can use this
file in the Quartus II block diagram editor.
<variation name>.cmp A VHDL component declaration file for the MegaCore function variation. Add the
contents of this file to any VHDL architecture that instantiates the MegaCore function.
<variation name>.html A MegaCore function report file in hypertext markup language format.
<variation name>.qip A single Quartus II IP file is generated that contains all of the assignments and other
information required to process your MegaCore function variation in the Quartus II
compiler. You are prompted to add this file to the current Quartus II project when you
exit from IP Toolbench.