Altera FIR Compiler - Manual (Page 22)

2–8 Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
FIR Compiler User Guide © May 2011 Altera Corporation
The generation report also lists the ports defined in the MegaCore function
variation file (
Figure 2–7 ). For a full description of the signals supported on
external ports for your MegaCore function variation, refer to Table 4–3 on
page 4–16 .
2. After you review the generation report, click Exit to close IP Toolbench. Then click
Yes on the Quartus II IP Files prompt to add the .qip file describing your custom
MegaCore function variation to the current Quartus II project.
Simulate the Design
To simulate your design in Verilog HDL or VHDL, use the IP functional simulation
models generated by IP Toolbench.
The IP functional simulation model is the .vo or .vho file (located in your design
directory) generated as specified in Step
1 on page 2–3 .
f
For more information about IP functional simulation models, refer to the Simulating
Altera Designs chapter in volume 3 of the Quartus II Handbook.
Simulating in ModelSim
A Tcl script (<variation name>_msim.tcl) is also generated which can be used to load
the VHDL testbench into the ModelSim simulator.
This script uses the file <variation name>_input.txt to provide input data to the FIR
filter. The output from the simulation is stored in a file <variation name>_output.txt.
Figure 2–7. Port Lists in the Generation Report