Altera I/O Buffer (ALTIOBUF) IP Core User Manual
Page 20
Name
Required
Description
io_config_update
No
Input port that feeds the
IO_CONFIG
update port
for user-driven dynamic delay chain. When
asserted, the serial load shift register bits feed the
parallel load register. The value is a 1-bit wire
shared among all I/O instances.
This port is available when the
USE_OUT_
DYNAMIC_DELAY_CHAIN1
or
USE_OUT_DYNAMIC_
DELAY_CHAIN2
parameter value is
TRUE.
oe[]
No
The output-enable source to the tri-state buffer.
Input port
[NUMBER_OF_CHANNELS - 1..0]
wide. When the
oe
port is asserted,
dataout
and
dataout_b
are enabled. When
oe
is deasserted,
both
dataout
and
dataout_b
are disabled. This
port is used only when the
USE_OE
parameter
value is
TRUE
. If omitted, the default is V
CC
.
seriesterminationcontrol[]
No
Receives the current state of the pull up and pull
down
Rs
control buses from a termination logic
block. Input port
[WIDTH_STC * NUMBER_OF_
CHANNELS - 1..0]
wide.
Port is available only when the
USE_TERMINA-
TION_CONTROL
parameter value is
TRUE.
seriesterminationcontrol_b
No
Receives the current state of the pull up and pull
down
Rs
control buses from a termination logic
block. Input port
[WIDTH_STC * NUMBER_OF_
CHANNELS - 1..0]
wide.
Port is available only when the
USE_DIFFEREN-
TIAL_MODE
parameter value is
TRUE.
parallelterminationcontrol[]
No
Receives the current state of the pull up and pull
down
Rt
control buses from a termination logic
block. Input port
[WIDTH_PTC * NUMBER_OF_
CHANNELS - 1..0]
wide. The port is available
for Stratix III device families only. Supported in
Stratix
®
series only.
Port is available only when the
USE_TERMINA-
TION_CONTROL
parameter value is
TRUE.
20
ALTIOBUF Signals and Parameters: As Output Buffer
UG-01024
2014.12.15
Altera Corporation
I/O Buffer (ALTIOBUF) IP Core User Guide