Altera I/O Buffer (ALTIOBUF) IP Core User Manual
Page 24
Name
Required
Description
io_config_clk
No
Input clock port that feeds the
IO_CONFIG
for user-
driven dynamic delay chain. The maximum
frequency for this clock is 30 MHz. Input port used as
the clock signal of shift register block. The value is a
1-bit wire shared among all I/O instances.
This port is available only if the
USE_IN_DYNAMIC_
DELAY_CHAIN
,
USE_OUT_DYNAMIC_DELAY_CHAIN1
, or
USE_OUT_DYNAMIC_DELAY_CHAIN2
parameter value is
TRUE
.
io_config_clkena[]
No
Input clock-enable that feeds the ena port of
IO_
CONFIG
for user-driven dynamic delay chain. Input
port
[NUMBER_OF_CHANNELS - 1..0]
wide. Input
port used as the clock signal of the shift register block.
This port is available only if the
USE_IN_DYNAMIC_
DELAY_CHAIN
,
USE_OUT_DYNAMIC_DELAY_CHAIN1
, or
USE_OUT_DYNAMIC_DELAY_CHAIN2
parameter value is
TRUE
.
io_config_update
No
Input port that feeds the
IO_CONFIG
update port for
user-driven dynamic delay chain. When asserted, the
serial load shift register bits feed the parallel load
register. The value is a 1-bit wire shared among all I/
O instances.
This port is available only if the
USE_IN_DYNAMIC_
DELAY_CHAIN
,
USE_OUT_DYNAMIC_DELAY_CHAIN1
, or
USE_OUT_DYNAMIC_DELAY_CHAIN2
parameter value is
TRUE
.
oe[]
Yes
The output-enable source to the tri-state buffer. Input
port
[NUMBER_OF_CHANNELS - 1..0]
wide. If
omitted, the default is V
CC
.
oe_b
No
The output-enable source to the tri-state buffer. Input
port
[NUMBER_OF_CHANNELS - 1..0]
wide. If
omitted, the default is V
CC
. Port is available only
when the
USE_DIFFERENTIAL_MODE
parameter value
is
TRUE
.
24
ALTIOBUF Signals and Parameters: As Bidirectional Buffer
UG-01024
2014.12.15
Altera Corporation
I/O Buffer (ALTIOBUF) IP Core User Guide