Altera I/O Buffer (ALTIOBUF) IP Core - Manual (Page 6)

for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example
design for hardware testing.
5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate >
Generate Testbench System is not available for some IP cores.
6. To generate a top-level HDL design example for hardware verification, click Generate > HDL
Example. Generate > HDL Example is not available for some IP cores.
When you generate the IP variation with a Quartus II project open, the parameter editor automatically
adds the IP variation to the project. Alternatively, click Project > Add/Remove Files in Project to
manually add a top-level .qip or .qsys IP variation file to a Quartus II project. To fully integrate the IP
into the design, make appropriate pin assignments to connect ports. You can define a virtual pin to
avoid making specific pin assignments to top-level signals.
Note: By default, all unused pins are tied to ground. Altera recommends setting all unused pins to tri-
state because doing otherwise might cause interference. To set all unused pins to tri-state, in the
Quartus II software, click Assignments > Device > Device and Pin Options > Unused Pins
and select an item from the Reserve all unused pins list.
Upgrading IP Cores
IP core variants generated with a previous version of the Quartus II software may require upgrading
before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to
identify and upgrade IP core variants.
The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or
unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can
compile the IP variation in the current version of the Quartus II software. Many Altera IP cores support
automatic upgrade.
The upgrade process renames and preserves the existing variation file (
.v , . sv , or .vhd ) as <my_variant> _
BAK.v , .sv , .vhd in the project directory.
Table 1: IP Core Upgrade Status
IP Core Status Corrective Action
Required Upgrade IP
Components
You must upgrade the IP variation before compiling in the current version of
the Quartus II software.
Optional Upgrade IP
Components
Upgrade is optional for this IP variation in the current version of the Quartus
II software. You can upgrade this IP variation to take advantage of the latest
development of this IP core. Alternatively you can retain previous IP core
characteristics by declining to upgrade.
Upgrade Unsupported Upgrade of the IP variation is not supported in the current version of the
Quartus II software due to IP core end of life or incompatibility with the
current version of the Quartus II software. You are prompted to replace the
obsolete IP core with a current equivalent IP core from the IP Catalog.
6 Upgrading IP Cores
UG-01024
2014.12.15
Altera Corporation I/O Buffer (ALTIOBUF) IP Core User Guide
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