Altera Signal Integrity Development Kit, Stratix V GX Edition - Manual (Page 13)

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit
Stratix V GX Edition User Guide
4. Development Board Setup
The instructions in this chapter explain how to set up the Stratix V GX transceiver
signal integrity development board.
Setting Up the Board
To prepare and apply power to the board, perform the following steps:
1. The Stratix V GX transceiver signal integrity development board ships with its
board switches preconfigured to support the design examples in the kit. If you
suspect your board might not be currently configured with the default settings,
follow the instructions in
“Factory Default Switch Settings” on page 4–2 to return
the board to its factory settings before proceeding.
2. The transceiver signal integrity development board ships with design examples
stored in the flash memory device. Verify the Load Selector (J28) is set to the jump
pins 2-3 position to load the design stored in the factory portion of flash memory.
Figure 4–1 shows the switch location on the Stratix V GX transceiver signal
integrity development board. Connect the 120 W, 20 VDC @ 6.32 A power supply
(model # LTE120E-SW-3XX) to the DC Power Jack (J1) on the FPGA board and
plug the cord into a power outlet.
c Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage.
3. Set the POWER switch (SW1) to the on position. When power is supplied to the
board, Power blue LED (D3) illuminates indicating that the board has power.
The MAX II device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The Load Selector (J28) controls which design to
load: When in the jump pins 2-3 position, the PFL loads the design from the factory
portion of flash memory. When in the jump pins 1-2 position, the PFL loads the design
from the user portion of flash memory.
1 The kit includes a MAX II design which contains the MAX II PFL megafunction. The
design resides in the <install dir>\kits\stratixVGX_5sgxea7nf40_si\examples\max2
directory.
When configuration is complete, one of two LEDs illuminate, (D10 for FACTORY_IMAGE
or D11 for USER_IMAGE) signaling that the Stratix V GX device configured successfully.
If either configuration fails, the CONFIG_ERR LED (D9) illuminates.
f
For more information about the PFL megafunction, refer to AN 386: Parallel Flash
Loader Megafunction User Guide .