Altera Signal Integrity Development Kit, Stratix V GX Edition - Manual (Page 42)

6–22 Chapter 6: Board Test System
Configuring the FPGA Using the Quartus II Programmer
Transceiver Signal Integrity Development Kit July 2012 Altera Corporation
Stratix V GX Edition User Guide
Serial Port Registers
The Serial port registers control shows the current values from the Si570 registers.
f For more information about the Si570 registers, refer to the Si570/Si571 data sheet
available on the Silicon Labs website (
www.silabs.com ).
fXTAL
The fXTAL control shows the calculated internal fixed-frequency crystal, based on the
serial port register values.
f For more information about the f
XTAL
value and how it is calculated, refer to the
Si570/Si571 data sheet available on the Silicon Labs website ( www.silabs.com ).
Target Frequency
The Target frequency control allows you to specify the frequency of the clock. Legal
values are between 10 and 945 MHz and select frequencies to 1400 MHz. For example,
421.31259873 is possible within 100 parts per million (ppm). The Target frequency
control works in conjunction with the Set New Frequency control.
Reset Si570
The clear control sets the Si570 programmable oscillator to the default frequency as
follows:
Y3 = 644.53125 MHz
Y4 = 706.25 MHz
Y5 = 625 MHz
Y6 = 875 MHz
Set New Frequency
The Set New Frequency control sets the Si570 programmable oscillator frequency to
the value in the Target frequency control. Frequency changes might take several
milliseconds to take effect. You might see glitches on the clock during this time. Altera
recommends resetting the FPGA logic after changing frequencies.
Configuring the FPGA Using the Quartus II Programmer
You can use the Quartus II Programmer to configure the FPGA with a specific .sof.
Before configuring the FPGA, ensure that the Quartus II Programmer and the
USB-Blaster driver are installed on the host computer, the USB cable is connected to
the transceiver signal integrity development board, power to the board is on, and no
other applications that use the JTAG chain are running.
1 If you connect an external USB-Blaster download cable and power cycle the board, the
on-board Blaster is disconnected and the S5_UNLOCK function (
Table 4–3 on
page 4–4 ) does not allow JTAG access to the FPGA. To successfully use the USB-
Blaster cable, disconnect it before power cycling the board. After you power cycled
the board, then reconnect the USB-Blaster cable.