Altera Signal Integrity Development Kit, Stratix V GX Edition - Manual (Page 32)

6–12 Chapter 6: Board Test System
Using the Board Test System
Transceiver Signal Integrity Development Kit July 2012 Altera Corporation
Stratix V GX Edition User Guide
2. Connect differential clock cables from SMAs J72/73 to J79/J80.
The following sections describe the controls on the XFP/SFP+ tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■ Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded. Channel lock will always display
NOT locked for single channel designs.
■ Pattern sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Port
Use the following controls to select an interface to apply PMA settings, data type and
error control:
Figure 6–6. The XFP/SFP+ Tab