Altera Cyclone V SoC Development Board - Manual (Page 18)

2–10 Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
Cyclone V SoC Development Board November 2013 Altera Corporation
Reference Manual
D12 PGM_CONFIG 2.5-V Load the flash memory image identified by the PGM LEDs
B14 PGM_LED0 2.5-V Flash memory PGM select indicator 0
C13 PGM_LED1 2.5-V Flash memory PGM select indicator 1
B16 PGM_LED2 2.5-V Flash memory PGM select indicator 2
B13 PGM_SEL 2.5-V Toggles the PGM_LED[2:0] LED sequence
C11 QSPI_RESETN 2.5-V Reset signal to QSPI flash
P13 RST 1.8-V Reset input
D5 SDI_RX_BYPASS 2.5-V SDI equalizer bypass enable
E8 SDI_RX_EN 2.5-V SDI RX enable
D11 SDI_TX_EN 2.5-V SDI TX enable
R12 SECURITY_MODE 1.8-V
DIP switch for the embedded USB-Blaster II to send FACTORY
command at power up
A10 SI570_EN 2.5-V Si570 programmable clock enable
D4 SI571_EN 2.5-V Si571 programmable clock enable
R16 TRST 1.8-V Reset output
H5 USB_B2_CLK 2.5-V Embedded USB-Blaster II interface clock
R4 USB_CFG0 1.8-V Embedded USB-Blaster II interface (reserved for future use)
T4 USB_CFG1 1.8-V Embedded USB-Blaster II interface (reserved for future use)
P8 USB_CFG2 1.8-V Embedded USB-Blaster II interface (reserved for future use)
T7 USB_CFG3 1.8-V Embedded USB-Blaster II interface (reserved for future use)
N8 USB_CFG4 1.8-V Embedded USB-Blaster II interface (reserved for future use)
R8 USB_CFG5 1.8-V Embedded USB-Blaster II interface (reserved for future use)
T8 USB_CFG6 1.8-V Embedded USB-Blaster II interface (reserved for future use)
T9 USB_CFG7 1.8-V Embedded USB-Blaster II interface (reserved for future use)
R9 USB_CFG8 1.8-V Embedded USB-Blaster II interface (reserved for future use)
P9 USB_CFG9 1.8-V Embedded USB-Blaster II interface (reserved for future use)
M8 USB_CFG10 1.8-V Embedded USB-Blaster II interface (reserved for future use)
T10 USB_CFG11 1.8-V Embedded USB-Blaster II interface (reserved for future use)
A11 USB_RESET 2.5-V Embedded USB-Blaster II interface reset
Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 4 of 4)
Board
Reference (U19)
Schematic Signal Name I/O Standard Description