Altera Cyclone V SoC Development Board - Manual (Page 50)

2–42 Chapter 2: Board Components
Memory
Cyclone V SoC Development Board November 2013 Altera Corporation
Reference Manual
T7 DDR3_HPS_A14 H25 1.5-V SSTL Class I Address bus
M2 DDR3_HPS_BA0 E29 1.5-V SSTL Class I Bank address bus
N8 DDR3_HPS_BA1 J24 1.5-V SSTL Class I Bank address bus
M3 DDR3_HPS_BA2 J23 1.5-V SSTL Class I Bank address bus
K3 DDR3_HPS_CASN E27 1.5-V SSTL Class I Row address select
K9 DDR3_HPS_CKE L29 1.5-V SSTL Class I Column address select
J7 DDR3_HPS_CLK_P L23
Differential 1.5-V
SSTL Class I
Differential output clock
K7 DDR3_HPS_CLK_N M23
Differential 1.5-V
SSTL Class I
Differential output clock
L2 DDR3_HPS_CSN H24 1.5-V SSTL Class I Chip select
E7 DDR3_HPS_DM4 W27 1.5-V SSTL Class I Write mask byte lane
F7 DDR3_HPS_DQ32 W26 1.5-V SSTL Class I Data bus
H7 DDR3_HPS_DQ33 R24 1.5-V SSTL Class I Data bus
F2 DDR3_HPS_DQ34 U27 1.5-V SSTL Class I Data bus
E3 DDR3_HPS_DQ35 V28 1.5-V SSTL Class I Data bus
H3 DDR3_HPS_DQ36 T25 1.5-V SSTL Class I Data bus
G2 DDR3_HPS_DQ37 U25 1.5-V SSTL Class I Data bus
H8 DDR3_HPS_DQ38 V27 1.5-V SSTL Class I Data bus
F8 DDR3_HPS_DQ39 Y29 1.5-V SSTL Class I Data bus
F3 DDR3_HPS_DQS_P4 T24
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 4
G3 DDR3_HPS_DQS_N4 T23
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 4
K1 DDR3_HPS_ODT H28 1.5-V SSTL Class I On-die termination enable
J3 DDR3_HPS_RASN D30 1.5-V SSTL Class I Row address select
T2 DDR3_HPS_RESETN P30 1.5-V SSTL Class I Reset
L3 DDR3_HPS_WEN C28 1.5-V SSTL Class I Write enable
L8 DDR3_HPS_ZQ01 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U22)
N3 DDR3_HPS_A0 F26 1.5-V SSTL Class I Address bus
P7 DDR3_HPS_A1 G30 1.5-V SSTL Class I Address bus
P3 DDR3_HPS_A2 F28 1.5-V SSTL Class I Address bus
N2 DDR3_HPS_A3 F30 1.5-V SSTL Class I Address bus
P8 DDR3_HPS_A4 J25 1.5-V SSTL Class I Address bus
P2 DDR3_HPS_A5 J27 1.5-V SSTL Class I Address bus
R8 DDR3_HPS_A6 F29 1.5-V SSTL Class I Address bus
R2 DDR3_HPS_A7 E28 1.5-V SSTL Class I Address bus
T8 DDR3_HPS_A8 H27 1.5-V SSTL Class I Address bus
Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)
Board
Reference
Schematic
Signal Name
Cyclone V SoC
Pin Number
I/O Standard Description