Hsmc, Hsmc –30 – Altera Cyclone V SoC Development Board User Manual
Page 38
2–30
Chapter 2: Board Components
Components and Interfaces
Cyclone V SoC Development Board
November 2013
Altera Corporation
Reference Manual
HSMC
The development board supports a HSMC interface (J12). The HSMC interface
supports a full SPI4.2 interface (17 LVDS channels), two input and output clocks, as
well as JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or
LVDS.
1
The HSMC is an Altera-developed open specification, which allows you to expand
the functionality of the development board through the addition of daughtercards
(HSMCs).
f
For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, and mechanical information, refer to the
manual.
The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series. Since the Cyclone V SoC
development board is not a transceiver board, the transceiver pins of the HSMC is not
connected to the Cyclone V SoC device.
39
ENET2_RX_DV
Transmit mode for PHY1
Pulled high
53
ENET1_RX_D0
Auto-negotiation disabled.
10 base-T default.
Pulled low
53
ENET1_RX_D0
Address for SMI
Pulled low
54
ENET1_RX_D1
Address for SMI
Pulled low
Table 2–22. Ethernet PHY (FPGA) Bootstrap Encoding Scheme
Board Reference
(U11)
Schematic Signal Name
Description
Strapping Option