Flash memory device, Flash memory device –5 – Altera Nios Development Board User Manual

Page 13

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Altera Corporation

1–5

December 2004

Nios Development Board Reference Manual, Cyclone Edition

Board Components

The development board provides two separate methods for configuring
the Cyclone device:

1.

Using the Quartus II software running on a host computer, a
designer configures the device directly via an Altera download
cable connected to the Cyclone JTAG header (J24).

2.

When power is applied to the board, a configuration controller
device (U3) attempts to configure the Cyclone device with hardware
configuration data stored in flash memory. For more information on
the configuration controller, see

“Configuration Controller Device

(EPM7128AE)” on page 1–20

.

f

See the Altera Cyclone literature page for Cyclone-related
documentation at www.altera.com/literature/lit-cyc.html including a
Cyclone EP1C20 pinout document.

Flash Memory
Device

U5 is an 8 Mbyte AMD AM29LV065D flash memory device connected to
the Cyclone device and can be used for two purposes:

3.

A Nios II embedded processor implemented on the Cyclone device
can use the flash memory as general-purpose readable memory and
non-volatile storage.

4.

The flash memory can hold Cyclone configuration data that is used
by the configuration controller to load the Cyclone device at power-
up. See

“Configuration Controller Device (EPM7128AE)” on

page 1–20

for related information.

Hardware configuration data that implements the Nios II reference
design is pre-stored in this flash memory. The pre-loaded Nios II
reference design, once loaded, can identify the 8 Mbyte flash memory in
its address space, and can program new data (either new Cyclone
configuration data, Nios II embedded processor software, or both) into
flash memory. The Nios II embedded processor software includes
subroutines for writing and erasing this specific type of AMD flash
memory.

The flash memory device shares address and data connections with the
SRAM chips and the Ethernet MAC/PHY chip. For shared bus
information, see

“Shared Bus Table” on page A–1

.

f

See www.amd.com for detailed information about the flash memory
device.

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