Altera Nios Development Board - Manual (Page 32)

1–24 Altera Corporation
Nios Development Board Reference Manual, Cyclone Edition December 2004
Configuration Controller Device (EPM7128AE)
hardware image. Nios II development tools documentation on how to
create your own user hardware image data and several facilities for
burning your user hardware image into flash memory.
Safe Hardware Image
If there is no valid user hardware image, or if SW9 (Force Safe) is pressed,
the configuration controller begins reading data out of flash at address
0x700000. Any FPGA configuration data stored at this location is
conventionally called the safe hardware image. Your development board
was factory-programmed with a safe hardware image, plus additional
data located in the range 0x700000-0x7FFFFF, as shown in
Table 1–7 on
page 1–25 .
1 The Nios II development kit includes the source files for the
factory-programmed reference design.
The configuration controller will stop reading data when the FPGA
successfully configures. The safe example design is setup to begin
executing code from address 0x7B0000. This region of flash memory is
factory-programmed with the web-server application software.
1 Do Not Erase your safe hardware image (safe hardware
configuration data). If you do so inadvertently, see “Restoring
the Factory Configuration” on page B–1 for instructions on how
to restore your board to its factory configuration.