Altera Nios Development Board - Manual (Page 37)

Altera Corporation 1–29
December 2004 Nios Development Board Reference Manual, Cyclone Edition
Board Components
A socketed 50 MHz free-running oscillator (Y2) supplies the fundamental
operating frequency, and a clock buffer (U2) drives zero-skew clock
signals to various points on the board.
The Cyclone device can synthesize a new clock signal internally using on-
chip PLLs, and distribute the clock to various locations on the board by
outputting the clock signal to the IO_PLL1_OUT0_p pin. The clock buffer
drives this signal to the following locations:
■ The PROTO1_CLKIN and PROTO2_CLKIN pins on the expansion
prototype connectors, allowing a user-defined clock to drive each of
the expansion prototype headers.
■ The clock input for the SDRAM memory (U57), allowing SDRAM to
run at a different rate than the clock oscillator.
■ The CLK0 clock input on the Cyclone device.
The Cyclone device can also supply a clock from the IO_PLL2_OUT0_p
pin to the SDRAM (U57).
1 The 50 MHz oscillator (Y2) is socketed and can be changed by
the user. However, the EPM7128AE device configuration control
circuit and other Altera reference designs are not guaranteed to
work at different frequencies. It is the user’s responsibility to
accommodate a new clock oscillator when designing a system.
JTAG Connectors The Nios development board, has three 10-pin JTAG headers (J24, J5 and
J28) compatible with Altera download cables such as the USB Blaster
m .
Each JTAG header connects to one Altera device and forms a single-
device JTAG chain. J24 connects to the Cyclone device (U60), J5 connects
into the EPM7128AE device (U3), and J28 connects to the EPCS4 serial-
configuration device (U59).
JTAG Connector to Cyclone Device (J24)
J24 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the
Cyclone device (U60) as shown in
Figure 1–22 . Altera Quartus II software
can directly configure the Cyclone device with a new hardware image via
an Altera download cable as shown in
Figure 1–23 . In addition, the
Nios II IDE can access the Nios II processor’s JTAG debug module via a
download cable connected to the J24 JTAG connector.