Altera Nios Development Board User Manual
Page 17
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Altera Corporation
1–9
December 2004
Nios Development Board Reference Manual, Cyclone Edition
Board Components
The SDRAM device pins are connected to the Cyclone device (see
). An SDRAM controller peripheral is included with
the Nios II development kit, allowing a Nios II processor to view the
SDRAM device as a large, linearly-addressable memory.
Table 1–3. SDRAM (U57) Pin Table (Part 1 of 2)
Pin Name
Pin Number
Connects to Cyclone Pin
A0
25
M2
A1
26
M1
A2
27
M6
A3
60
M4
A4
61
J8
A5
62
J7
A6
63
J6
A7
64
J5
A8
65
J4
A9
66
J3
A10
24
H6
A11
21
H5
BA0
22
H7
BA1
23
H1
DQ0
2
M5
DQ1
4
M3
DQ2
5
M7
DQ3
7
N6
DQ4
8
N1
DQ5
10
N2
DQ6
11
N4
DQ7
13
N3
DQ8
74
N5
DQ9
76
N7
DQ10
77
P7
DQ11
79
P2
DQ12
80
P1
DQ13
82
P6
DQ14
83
P5
DQ15
85
P3
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