Intel OCPRF100 MP - Manual (Page 132)

OCPRF100 MP Server System Technical Product Specification
Revision 1.0
125
10.2.7.1 Resetting the System
The FPC has the capability to reset the entire system (processors, chip sets, etc.) by asserting
the HARD_RESET signal. It must be asserted for a minimum of 500 ms. There is no maximum.
10.2.7.2 Reset Inputs
The state of the reset switch can be determined by reading the RST_SWT_LATCH signal within
the PLD. If the reset switch has been asserted since the previous reading of this latch, then the
latch will be asserted (high). Reading of this latch clears the latch. Therefore, there are no mini-
mum polling requirements to detect an asserted switch. The latch is asynchronously set when-
ever the switch is pressed and remains set as long as the switch is pressed, whether or not the
latch is read by the FPC.
10.2.7.3 Reset Switch During +5 V Power Cycle
While +5 V power is inactive, the RST_SWT_LATCH remains asserted. This is because the reset
switch circuitry incorporates a pull-up to main +5 V, and when main power is off, the main +5 V
power is at 0 V, making the switch appear asserted. This pull-up is tied to main +5 V to save
power on +5 V standby.
The RST_SWT_LATCH might remain asserted up to and including the first read after the
PWR_GOOD indicates that main +5 V power is valid. The first valid RST_SWT_LATCH read
occurs on the SECOND READ after PWR_GOOD becomes asserted (high).
10.2.7.4 Resetting the FPC
The FPC is reset whenever the VCC_STDBY is invalid and 500 ms (typically) after VCC_STDBY
becomes valid. The front panel has development support for a push button reset input. Removing
the default RP1A1 and connecting a switch between J1A1 pins 3 and 4 activates this by control-
ling the PUSH_BTN_RST_L signal.
10.2.7.5 Determining the System Reset State
Signal PROC_RESET _LATCH provides firmware with an indication of the processor reset state.
A latch is used because a processor reset assertion may last as short a period of time as 40 ns,
and as long as many seconds. Therefore, an assertion of the PROC_RESET_L signal causes
the PROC_RESET _LATCH to become set. When the signal is read by the FPC, the latch is
cleared (assuming the PROC_RESET_L signal is no longer asserted).
To determine whether an assertion of the PROC_RESET_L signal has occured since the last
reset and the current state, read the PROC_RESET_LATCH twice. If PROC_RESET_LATCH
returns sequential ones, then the processors are currently in reset. If PROC_RESET_LATCH
returns one, then zero, the processors have gone through reset since the last time the latch was
read, but are not currently in reset. If PROC_RESET_L returns two zeroes, the processors have
not gone through reset since the last time the latch was read.
Whenever the front panel goes through a hardware reset this latch is cleared.