Intel OCPRF100 MP - Manual (Page 77)

OCPRF100 MP Server System Technical Product Specification
Revision 1.0
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If the boot strap processor (BSP) fails during POST, BIOS will attempt to boot the system using
another processor. This feature is called fault resilient booting (FRB). For additional information
on FRB, see the OPRF100 MP Board Set Technical Product Specification.
6.1.2 Profusion
®
Chip Set
The Profusion PCIset connects the processors, memory, and four peer PCI buses. It consists of
the memory access controller (MAC), data interface buffer (DIB), and PCI host bridge (PB64).
The OCPRF100 MP server system BIOS supports the following features of the chip set:
• Memory port interleaving
• Coherency filters
• Coherency rules SRAM
• Routing of memory cycles for PCI, VGA, APICs, and ROM space
• Routing of I/O cycles
• System management RAM (SMRAM)
• Bus ECC
• Memory ECC
Memory gaps from 512KB to 640KB and from 15 MB to 16 MB are not supported. The memory in
these regions is treated as normal system memory; memory-mapped I/O resources cannot be
placed there.
BIOS automatically initializes system memory, the coherency filters, and the rules SRAM. It
examines the PC-100 serial presence detect (SPD) EEPROMs on the PC-100 DIMMs and
adjusts the memory timings accordingly. Three levels of memory tests accommodate different
preferences about test time versus thoroughness. For higher availability, BIOS can deconfigure a
failing memory DIMM, memory port, and coherency filter.
6.1.3 I/O Subsystem
The OPRF100 I/O carrier provides a PC-AT compatible I/O subsystem with PCI slots instead of
ISA/EISA slots. It provides 10 PCI slots, an embedded PCI VGA, and an embedded dual-channel
LVDS controller. It also supports the standard compatibility devices: two serial ports, one parallel
port, two USB ports, an IDE port, a floppy controller, and a PS/2 keyboard and mouse.
The PIIX4E provides the bridge to ISA-compatible resources on the I/O carrier. It also provides
an IDE controller and a USB controller. BIOS uses its SMBus to access the SPD EEPROMs on
the PC-100 DIMMs. BIOS uses the 256 bytes of CMOS configuration RAM for nonvolatile stor-
age of BIOS Setup options and other BIOS parameters.
The SMC* Ultra I/O chip (FDC37C937APM) provides a floppy controller, parallel port, two serial
ports, a keyboard port, and a mouse port. The BIOS supports four modes of the parallel port: out-
put-only, bidirectional, enhanced parallel port (EPP), and extended capabilities port (ECP). The