Intel 253666-024US User Manual
Volume 2a: instruction set reference, a-m
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Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 2A:
Instruction Set Reference, A-M
NOTE:
The Intel 64 and IA-32 Architectures Software Developer's Manual
consists of five volumes: Basic Architecture, Order Number 253665;
Instruction Set Reference A-M, Order Number 253666; Instruction Set
Reference N-Z, Order Number 253667; System Programming Guide,
Part 1, Order Number 253668; System Programming Guide, Part 2,
Order Number 253669. Refer to all five volumes when evaluating your
design needs.
Order Number: 253666-024US
August 2007
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Table of contents
Document Outline
- Chapter 1 About This Manual
- Chapter 2 Instruction Format
- Chapter 3 Instruction Set Reference, A-M
- 3.1 Interpreting the Instruction Reference Pages
- 3.1.1 Instruction Format
- 3.1.1.1 Opcode Column in the Instruction Summary Table
- 3.1.1.2 Instruction Column in the Opcode Summary Table
- 3.1.1.3 64-bit Mode Column in the Instruction Summary Table
- 3.1.1.4 Compatibility/Legacy Mode Column in the Instruction Summary Table
- 3.1.1.5 Description Column in the Instruction Summary Table
- 3.1.1.6 Description Section
- 3.1.1.7 Operation Section
- 3.1.1.8 Intel® C/C++ Compiler Intrinsics Equivalents Section
- 3.1.1.9 Flags Affected Section
- 3.1.1.10 FPU Flags Affected Section
- 3.1.1.11 Protected Mode Exceptions Section
- 3.1.1.12 Real-Address Mode Exceptions Section
- 3.1.1.13 Virtual-8086 Mode Exceptions Section
- 3.1.1.14 Floating-Point Exceptions Section
- 3.1.1.15 SIMD Floating-Point Exceptions Section
- 3.1.1.16 Compatibility Mode Exceptions Section
- 3.1.1.17 64-Bit Mode Exceptions Section
- 3.1.1 Instruction Format
- 3.2 Instructions (A-M)
- AAA-ASCII Adjust After Addition
- AAD-ASCII Adjust AX Before Division
- AAM-ASCII Adjust AX After Multiply
- AAS-ASCII Adjust AL After Subtraction
- ADC-Add with Carry
- ADD-Add
- ADDPD-Add Packed Double-Precision Floating-Point Values
- ADDPS-Add Packed Single-Precision Floating-Point Values
- ADDSD-Add Scalar Double-Precision Floating-Point Values
- ADDSS-Add Scalar Single-Precision Floating-Point Values
- ADDSUBPD-Packed Double-FP Add/Subtract
- ADDSUBPS-Packed Single-FP Add/Subtract
- AND-Logical AND
- ANDPD-Bitwise Logical AND of Packed Double-Precision Floating- Point Values
- ANDPS-Bitwise Logical AND of Packed Single-Precision Floating-Point Values
- ANDNPD-Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
- ANDNPS-Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
- ARPL-Adjust RPL Field of Segment Selector
- BOUND-Check Array Index Against Bounds
- BSF-Bit Scan Forward
- BSR-Bit Scan Reverse
- BSWAP-Byte Swap
- BT-Bit Test
- BTC-Bit Test and Complement
- BTR-Bit Test and Reset
- BTS-Bit Test and Set
- CALL-Call Procedure
- CBW/CWDE/CDQE-Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword
- CLC-Clear Carry Flag
- CLD-Clear Direction Flag
- CLFLUSH-Flush Cache Line
- CLI - Clear Interrupt Flag
- CLTS-Clear Task-Switched Flag in CR0
- CMC-Complement Carry Flag
- CMOVcc-Conditional Move
- CMP-Compare Two Operands
- CMPPD-Compare Packed Double-Precision Floating-Point Values
- CMPPS-Compare Packed Single-Precision Floating-Point Values
- CMPS/CMPSB/CMPSW/CMPSD/CMPSQ-Compare String Operands
- CMPSD-Compare Scalar Double-Precision Floating-Point Values
- CMPSS-Compare Scalar Single-Precision Floating-Point Values
- CMPXCHG-Compare and Exchange
- CMPXCHG8B/CMPXCHG16B-Compare and Exchange Bytes
- COMISD-Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
- COMISS-Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
- CPUID-CPU Identification
- CVTDQ2PD-Convert Packed Doubleword Integers to Packed Double- Precision Floating-Point Values
- CVTDQ2PS-Convert Packed Doubleword Integers to Packed Single- Precision Floating-Point Values
- CVTPD2DQ-Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
- CVTPD2PI-Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
- CVTPD2PS-Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
- CVTPI2PD-Convert Packed Doubleword Integers to Packed Double- Precision Floating-Point Values
- CVTPI2PS-Convert Packed Doubleword Integers to Packed Single- Precision Floating-Point Values
- CVTPS2DQ-Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
- CVTPS2PD-Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
- CVTPS2PI-Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
- CVTSD2SI-Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
- CVTSD2SS-Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
- CVTSI2SD-Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
- CVTSI2SS-Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
- CVTSS2SD-Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
- CVTSS2SI-Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
- CVTTPD2PI-Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
- CVTTPD2DQ-Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
- CVTTPS2DQ-Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
- CVTTPS2PI-Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
- CVTTSD2SI-Convert with Truncation Scalar Double-Precision Floating- Point Value to Signed Doubleword Integer
- CVTTSS2SI-Convert with Truncation Scalar Single-Precision Floating- Point Value to Doubleword Integer
- CWD/CDQ/CQO-Convert Word to Doubleword/Convert Doubleword to Quadword
- DAA-Decimal Adjust AL after Addition
- DAS-Decimal Adjust AL after Subtraction
- DEC-Decrement by 1
- DIV-Unsigned Divide
- DIVPD-Divide Packed Double-Precision Floating-Point Values
- DIVPS-Divide Packed Single-Precision Floating-Point Values
- DIVSD-Divide Scalar Double-Precision Floating-Point Values
- DIVSS-Divide Scalar Single-Precision Floating-Point Values
- EMMS-Empty MMX Technology State
- ENTER-Make Stack Frame for Procedure Parameters
- F2XM1-Compute 2x-1
- FABS-Absolute Value
- FADD/FADDP/FIADD-Add
- FBLD-Load Binary Coded Decimal
- FBSTP-Store BCD Integer and Pop
- FCHS-Change Sign
- FCLEX/FNCLEX-Clear Exceptions
- FCMOVcc-Floating-Point Conditional Move
- FCOMI/FCOMIP/ FUCOMI/FUCOMIP-Compare Floating Point Values and Set EFLAGS
- FCOS-Cosine
- FDECSTP-Decrement Stack-Top Pointer
- FDIV/FDIVP/FIDIV-Divide
- FDIVR/FDIVRP/FIDIVR-Reverse Divide
- FFREE-Free Floating-Point Register
- FICOM/FICOMP-Compare Integer
- FILD-Load Integer
- FINCSTP-Increment Stack-Top Pointer
- FINIT/FNINIT-Initialize Floating-Point Unit
- FIST/FISTP-Store Integer
- FISTTP-Store Integer with Truncation
- FLD-Load Floating Point Value
- FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ-Load Constant
- FLDCW-Load x87 FPU Control Word
- FLDENV-Load x87 FPU Environment
- FMUL/FMULP/FIMUL-Multiply
- FNOP-No Operation
- FPATAN-Partial Arctangent
- FPREM-Partial Remainder
- FPREM1-Partial Remainder
- FPTAN-Partial Tangent
- FRNDINT-Round to Integer
- FRSTOR-Restore x87 FPU State
- FSAVE/FNSAVE-Store x87 FPU State
- FSCALE-Scale
- FSIN-Sine
- FSINCOS-Sine and Cosine
- FSQRT-Square Root
- FST/FSTP-Store Floating Point Value
- FSTCW/FNSTCW-Store x87 FPU Control Word
- FSTENV/FNSTENV-Store x87 FPU Environment
- FSTSW/FNSTSW-Store x87 FPU Status Word
- FSUB/FSUBP/FISUB-Subtract
- FSUBR/FSUBRP/FISUBR-Reverse Subtract
- FTST-TEST
- FUCOM/FUCOMP/FUCOMPP-Unordered Compare Floating Point Values
- FXAM-ExamineModR/M
- FXCH-Exchange Register Contents
- FXRSTOR-Restore x87 FPU, MMX , XMM, and MXCSR State
- FXSAVE-Save x87 FPU, MMX Technology, SSE, and SSE2 State
- FXTRACT-Extract Exponent and Significand
- FYL2X-Compute y * log2x
- FYL2XP1-Compute y * log2(x +1)
- HADDPD-Packed Double-FP Horizontal Add
- HADDPS-Packed Single-FP Horizontal Add
- HLT-Halt
- HSUBPD-Packed Double-FP Horizontal Subtract
- HSUBPS-Packed Single-FP Horizontal Subtract
- IDIV-Signed Divide
- IMUL-Signed Multiply
- IN-Input from Port
- INC-Increment by 1
- INS/INSB/INSW/INSD-Input from Port to String
- INT n/INTO/INT 3-Call to Interrupt Procedure
- INVD-Invalidate Internal Caches
- INVLPG-Invalidate TLB Entry
- IRET/IRETD-Interrupt Return
- Jcc-Jump if Condition Is Met
- JMP-Jump
- LAHF-Load Status Flags into AH Register
- LAR-Load Access Rights Byte
- LDDQU-Load Unaligned Integer 128 Bits
- LDMXCSR-Load MXCSR Register
- LDS/LES/LFS/LGS/LSS-Load Far Pointer
- LEA-Load Effective Address
- LEAVE-High Level Procedure Exit
- LFENCE-Load Fence
- LGDT/LIDT-Load Global/Interrupt Descriptor Table Register
- LLDT-Load Local Descriptor Table Register
- LMSW-Load Machine Status Word
- LOCK-Assert LOCK# Signal Prefix
- LODS/LODSB/LODSW/LODSD/LODSQ-Load String
- LOOP/LOOPcc-Loop According to ECX Counter
- LSL-Load Segment Limit
- LTR-Load Task Register
- MASKMOVDQU-Store Selected Bytes of Double Quadword
- MASKMOVQ-Store Selected Bytes of Quadword
- MAXPD-Return Maximum Packed Double-Precision Floating-Point Values
- MAXPS-Return Maximum Packed Single-Precision Floating-Point Values
- MAXSD-Return Maximum Scalar Double-Precision Floating-Point Value
- MAXSS-Return Maximum Scalar Single-Precision Floating-Point Value
- MFENCE-Memory Fence
- MINPD-Return Minimum Packed Double-Precision Floating-Point Values
- MINPS-Return Minimum Packed Single-Precision Floating-Point Values
- MINSD-Return Minimum Scalar Double-Precision Floating-Point Value
- MINSS-Return Minimum Scalar Single-Precision Floating-Point Value
- MONITOR-Set Up Monitor Address
- MOV-Move
- MOV-Move to/from Control Registers
- MOV-Move to/from Debug Registers
- MOVAPD-Move Aligned Packed Double-Precision Floating-Point Values
- MOVAPS-Move Aligned Packed Single-Precision Floating-Point Values
- MOVD/MOVQ-Move Doubleword/Move Quadword
- MOVDDUP-Move One Double-FP and Duplicate
- MOVDQA-Move Aligned Double Quadword
- MOVDQU-Move Unaligned Double Quadword
- MOVDQ2Q-Move Quadword from XMM to MMX Technology Register
- MOVHLPS- Move Packed Single-Precision Floating-Point Values High to Low
- MOVHPD-Move High Packed Double-Precision Floating-Point Value
- MOVHPS-Move High Packed Single-Precision Floating-Point Values
- MOVLHPS-Move Packed Single-Precision Floating-Point Values Low to High
- MOVLPD-Move Low Packed Double-Precision Floating-Point Value
- MOVLPS-Move Low Packed Single-Precision Floating-Point Values
- MOVMSKPD-Extract Packed Double-Precision Floating-Point Sign Mask
- MOVMSKPS-Extract Packed Single-Precision Floating-Point Sign Mask
- MOVNTDQ-Store Double Quadword Using Non-Temporal Hint
- MOVNTI-Store Doubleword Using Non-Temporal Hint
- MOVNTPD-Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
- MOVNTPS-Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
- MOVNTQ-Store of Quadword Using Non-Temporal Hint
- MOVQ-Move Quadword
- MOVQ2DQ-Move Quadword from MMX Technology to XMM Register
- MOVS/MOVSB/MOVSW/MOVSD/MOVSQ-Move Data from String to String
- MOVSD-Move Scalar Double-Precision Floating-Point Value
- MOVSHDUP-Move Packed Single-FP High and Duplicate
- MOVSLDUP-Move Packed Single-FP Low and Duplicate
- MOVSS-Move Scalar Single-Precision Floating-Point Values
- MOVSX/MOVSXD-Move with Sign-Extension
- MOVUPD-Move Unaligned Packed Double-Precision Floating-Point Values
- MOVUPS-Move Unaligned Packed Single-Precision Floating-Point Values
- MOVZX-Move with Zero-Extend
- MUL-Unsigned Multiply
- MULPD-Multiply Packed Double-Precision Floating-Point Values
- MULPS-Multiply Packed Single-Precision Floating-Point Values
- MULSD-Multiply Scalar Double-Precision Floating-Point Values
- MULSS-Multiply Scalar Single-Precision Floating-Point Values
- MWAIT-Monitor Wait
- 3.1 Interpreting the Instruction Reference Pages