Intel 253666-024US - Manual (Page 470)

3-424 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State
INSTRUCTION SET REFERENCE, A-M
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384
XMM15 400
Reserved 416
Reserved 432
Reserved 448
Reserved 464
Reserved 480
Reserved 496
Table 3-52. Layout of the 64-bit-mode FXSAVE Map with
Default OperandSize
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CS FPU IP FOP FTW FSW FCW 0
MXCSR_MASK MXCSR Re-
served
DS FPU DP 16
Reserved ST0/MM0 32
Reserved ST1/MM1 48
Reserved ST2/MM2 64
Reserved ST3/MM3 80
Table 3-51. Layout of the 64-bit-mode FXSAVE Map
with Promoted OperandSize (Contd.)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0