Intel 253666-024US - Manual (Page 664)

3-618 Vol. 2A MOVD/MOVQ—Move Doubleword/Move Quadword
INSTRUCTION SET REFERENCE, A-M
#UD If CR0.EM[bit 2] = 1.
128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]
= 0. Execution of 128-bit instructions on a non-SSE2 capable
processor (one that is MMX technology capable) will result in the
instruction operating on the mm registers, not #UD.
If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.
#MF (MMX register operations only) If there is a pending FPU excep-
tion.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
Real-Address Mode Exceptions
#GP If any part of the operand lies outside of the effective address
space from 0 to FFFFH.
#UD If CR0.EM[bit 2] = 1.
128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]
= 0. Execution of 128-bit instructions on a non-SSE2 capable
processor (one that is MMX technology capable) will result in the
instruction operating on the mm registers, not #UD.
If the LOCK prefix is used.
#NM If CR0.TS[bit 3] = 1.
#MF (MMX register operations only) If there is a pending FPU excep-
tion.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0) If a memory address referencing the SS segment is in a non-
canonical form.
#GP(0) If the memory address is in a non-canonical form.