Intel 253666-024US User Manual
Page 79
Vol. 2A 3-33
INSTRUCTION SET REFERENCE, A-M
ADDPD—Add Packed Double-Precision Floating-Point Values
ADDPD—Add Packed Double-Precision Floating-Point Values
Description
Performs a SIMD add of the two packed double-precision floating-point values from
the source operand (second operand) and the destination operand (first operand),
and stores the packed double-precision floating-point results in the destination
operand.
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register. See Chapter 11 in the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1, for an overview of SIMD double-
precision floating-point operation.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
DEST[63:0] ← DEST[63:0] + SRC[63:0];
DEST[127:64] ← DEST[127:64] + SRC[127:64];
Intel C/C++ Compiler Intrinsic Equivalent
ADDPD
__m128d _mm_add_pd (m128d a, m128d b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
If a memory operand is not aligned on a 16-byte boundary,
regardless of segment.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
#NM
If CRO.TS[bit 3] = 1.
#XM
If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 58 /r
ADDPD xmm1,
xmm2/m128
Valid
Valid
Add packed double-precision floating-
point values from xmm2/m128 to
xmm1.