Intel 253666-024US - Manual (Page 691)

Vol. 2A 3-645
INSTRUCTION SET REFERENCE, A-M
MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask
MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign
Mask
Description
Extracts the sign bits from the packed double-precision floating-point values in the
source operand (second operand), formats them into a 2-bit mask, and stores the
mask in the destination operand (first operand). The source operand is an XMM
register, and the destination operand is a general-purpose register. The mask is
stored in the 2 low-order bits of the destination operand.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,
R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the
instruction to 64-bit operands. See the summary chart at the beginning of this
section for encoding data and limits.
Operation
DEST[0] ← SRC[63];
DEST[1] ← SRC[127];
IF DEST = r32
THEN DEST[31:2] ← ZeroExtend;
ELSE DEST[63:2] ← ZeroExtend;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
MOVMSKPD int _mm_movemask_pd ( __m128 a)
SIMD Floating-Point Exceptions
None.
Protected Mode Exceptions
#NM If CR0.TS[bit 3] = 1.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 50 /r MOVMSKPD r32,
xmm
Valid Valid Extract 2-bit sign mask
from xmm and store in r32.
66 REX.W 0F 50 /r MOVMSKPD r64,
xmm
Valid N.E. Extract 2-bit sign mask
from xmm and store in r64.
Zero extend 32-bit results
to 64-bits.