Intel 253666-024US - Manual (Page 314)

3-268 Vol. 2A DIVPD—Divide Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-M
DIVPD—Divide Packed Double-Precision Floating-Point Values
Description
Performs a SIMD divide of the two packed double-precision floating-point values in
the destination operand (first operand) by the two packed double-precision floating-
point values in the source operand (second operand), and stores the packed double-
precision floating-point results in the destination operand. The source operand can
be an XMM register or a 128-bit memory location. The destination operand is an XMM
register. See Chapter 11 in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 1, for an overview of a SIMD double-precision floating-point
operation.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[63:0] ← DEST[63:0] / (SRC[63:0]);
DEST[127:64] ← DEST[127:64] / (SRC[127:64]);
Intel C/C++ Compiler Intrinsic Equivalent
DIVPD __m128d _mm_div_pd(__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
If a memory operand is not aligned on a 16-byte boundary,
regardless of segment.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 5E /r DIVPD xmm1,
xmm2/m128
Valid Valid Divide packed double-precision floating-
point values in xmm1 by packed double-
precision floating-point values
xmm2/m128.