Intel 253666-024US - Manual (Page 211)

Vol. 2A 3-165
INSTRUCTION SET REFERENCE, A-M
CPUID—CPU Identification
MONITOR/MWAIT Leaf
5H EAX Bits 15-00: Smallest monitor-line size in bytes (default is processor's
monitor granularity)
Bits 31-16: Reserved = 0
EBX Bits 15-00: Largest monitor-line size in bytes (default is processor's
monitor granularity)
Bits 31-16: Reserved = 0
ECX Bits 00: Enumeration of Monitor-Mwait extensions (beyond EAX and
EBX registers) supported
Bits 01: Supports treating interrupts as break-event for MWAIT, even
when interrupts disabled
Bits 31 - 02: Reserved
EDX Bits 03 - 00: Number of C0* sub C-states supported using MWait
Bits 07 - 04: Number of C1* sub C-states supported using MWAIT
Bits 11 - 08: Number of C2* sub C-states supported using MWAIT
Bits 15 - 12: Number of C3* sub C-states supported using MWAIT
Bits 19 - 16: Number of C4* sub C-states supported using MWAIT
Bits 31 - 20: Reserved = 0
NOTE:
* The definition of C0 through C4 states for MWAIT extension are pro-
cessor-specific C-states, not ACPI C-states.
Thermal and Power Management Leaf
6H EAX
EBX
Bits 00: Digital temperature sensor is supported if set
Bits 01: Intel Dynamic Acceleration Enabled
Bits 31 - 02: Reserved
Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor
Bits 31 - 04: Reserved
ECX Bits 00: Hardware Coordination Feedback Capability (Presence of MCNT
and ACNT MSRs). The capability to provide a measure of delivered pro-
cessor performance (since last reset of the counters), as a percentage
of expected processor performance at frequency specified in CPUID
Brand String
Bits 31 - 01: Reserved = 0
EDX Reserved = 0
Architectural Performance Monitoring Leaf
Table 3-12. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value Information Provided about the Processor