Intel 253666-024US - Manual (Page 756)

3-710 Vol. 2A MWAIT—Monitor Wait
INSTRUCTION SET REFERENCE, A-M
MWAIT—Monitor Wait
Description
MWAIT instruction provides hints to allow the processor to enter an implementation-
dependent optimized state. There are two principal targeted usages: address-range
monitor and advanced power management. Both usages of MWAIT require the use of
the MONITOR instruction.
A CPUID feature flag (ECX bit 3; CPUID executed EAX = 1) indicates the availability
of MONITOR and MWAIT in the processor. When set, the unconditional execution of
MWAIT is supported at privilege levels 0; conditional execution is supported at privi-
lege levels 1 through 3 (test for the appropriate support before unconditional use).
The operating system or system BIOS may disable this instruction by using the
IA32_MISC_ENABLES MSR; disabling MWAIT clears the CPUID feature flag and
causes execution to generate an illegal opcode exception.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
MWAIT for Address Range Monitoring
For address-range monitoring, the MWAIT instruction operates with the MONITOR
instruction. The two instructions allow the definition of an address at which to wait
(MONITOR) and a implementation-dependent-optimized operation to commence at
the wait address (MWAIT). The execution of MWAIT is a hint to the processor that it
can enter an implementation-dependent-optimized state while waiting for an event
or a store operation to the address range armed by MONITOR.
ECX specifies optional extensions for the MWAIT instruction. EAX may contain hints
such as the preferred optimized state the processor should enter. For Pentium 4
processors (CPUID signature family 15 and model 3), non-zero values for EAX and
ECX are reserved.
A store to the address range armed by the MONITOR instruction, an interrupt, an NMI
or SMI, a debug exception, a machine check exception, the BINIT# signal, the INIT#
signal, or the RESET# signal will exit the implementation-dependent-optimized
state. Note that an interrupt will cause the processor to exit only if the state was
entered with interrupts enabled.
If a store to the address range causes the processor to exit, execution will resume at
the instruction following the MWAIT instruction. If an interrupt (including NMI)
caused the processor to exit the implementation-dependent-optimized state, the
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
OF 01 C9 MWAIT Valid Valid A hint that allow the processor to stop
instruction execution and enter an
implementation-dependent optimized state
until occurrence of a class of events.