Daq timing connections, Figure 39. extconv* signal timing, Daq timing connections -19 – National Instruments PCI-1200 User Manual
Page 41: Figure 3-9, Extconv* signal timing -19
Chapter 3
Signal Connections
© National Instruments Corporation
3-19
timing, and the other, 82C53(B), is available for general use. Use pins 38
through 40 and pin 43 to carry external signals for DAQ timing. These
signals are explained in the next section,
. Pins 41
through 48 carry general purpose timing signals from 82C53(B). These
signals are explained in the
General Purpose Timing Signal Connections
section later in this chapter.
DAQ Timing Connections
Each 82C53 counter/timer circuit contains three counters. Counter 0 on the
82C53(A) counter/timer, referred to as A0, is a sample-interval counter in
timed A/D conversions. Counter 1 on the 82C53(A) counter/timer, referred
to as A1, is a sample counter in controlled A/D conversions. Therefore,
counter A1 stops data acquisition after a predefined number of samples.
These counters are not available for general use.
Instead of counter A0, you can use EXTCONV* to externally time
conversions. Figure 3-9 shows the timing requirements for the
EXTCONV* input. An A/D conversion is initiated by a falling edge
on the EXTCONV*.
Figure 3-9. EXTCONV* Signal Timing
The external control signal EXTTRIG can either start a DAQ sequence or
terminate an ongoing DAQ sequence depending on the mode—posttrigger
(POSTTRIG) or pretrigger (PRETRIG). These modes are software
selectable.
In the POSTTRIG mode, EXTTRIG serves as an external trigger that
initiates a DAQ sequence. When you use counter A0 to time sample
intervals, a rising edge on EXTTRIG starts counter A0 and the DAQ
sequence. When you use EXTCONV* to time sample intervals, data
acquisition is enabled on a rising edge of EXTTRIG followed by a rising
edge on EXTCONV*. The first conversion occurs on the next falling edge
A/D Conversion starts within
125 ns from this point
t
w
250 ns minimum
t
w
t
w
EXTCONV*
V
IH
V
IL