Rainbow Electronics W90P710CDG User Manual
Page 272
W90P710CD/W90P710CDG
- 272 -
BITS
DESCRIPTIONS
[31:0] FIFO1SADDR
These bits indicate the source address of the bank location for the
LCD frame buffer in the system memory.
FIFO2 Start Address Register (FIFO2SADDR)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
FIFO2SADDR
0xFFF0_8034
R/W
FIFO2 start address
0x0000_0000
31
30
29
28
27
26
25
24
FIFO2SADDR[31:24]
23
22
21
20
19
18
17
16
FIFO2SADDR[23:16]
15
14
13
12
11
10
9
8
FIFO2SADDR[15:8]
7
6
5
4
3
2
1
0
FIFO2SADDR[7:0]
BITS
DESCRIPTIONS
[31:0] FIFO2SADDR
These bits indicate the source address of the bank location for the
LCD frame buffer in the system memory.
FIFO1 Request Count Register (FIFO1DREQCNT)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
FIFO1DREQCNT 0xFFF0_8038
R/W FIFO1 request count
0x0000_0000
31
30
29
28
27
26
25
24
FIFO1COLCNT[31:24]
23
22
21
20
19
18
17
16
FIFO1COLCNT[23:16]
15
14
13
12
11
10
9
8
FIFO1ROWCNT[15:8]
7
6
5
4
3
2
1
0
FIFO1ROWCNT[7:0]