Rainbow Electronics W90P710CDG User Manual
Page 302
W90P710CD/W90P710CDG
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BITS
DESCRIPTIONS
[31:30] Reserved Reserved
[29:20] VSPW
Vertical sync pulse width determines the VSYNC pulse's high level
width by counting the number of inactive lines.
[19:10] VBPD
Vertical back porch is the number of inactive lines at the start of a
frame, after vertical synchronization period.
[9:0] VFPD
Vertical front porch is the number of inactive lines at the end of a
frame, before vertical synchronization period.
LCD Timing Control 4 Register (LCDTCON4)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
LCDTCON4 0xFFF0_80BC
R/W LCD Timing Control 4
0x0000_0000
31
30
29
28
27
26
25
24
Reserved PCD[9:7]
23
22
21
20
19
18
17
16
PCD[6:0] Reserved
15
14
13
12
11
10
9
8
Reserved PLLRDY
7
6
5
4
3
2
1
0
LCDPRESC CLKSEL
BITS
DESCRIPTIONS
[31:27] Reserved
Reserved
[26:17]
PCD
The ten-bit PCD field is used to derive the LCD panel clock
frequency VCLK from LCD controller clock:
VCLK=LCDCLK/(PCD+2)
[16:9]
Reserved
Reserved
[8]
PLLRDY
Indicate LCDC that PLL is ready, can switch pixel clock source to
PLL clock
[7:1]
LCDPRESC
These bits pre-scale counter the LCD controller clock
Scale_CLK = PLL_FIN / ( 2*( LCDPRESC + 1 ) )
[0] CLKSEL
This bit driver the LCD controller clock source.
0 = external PLL clock 1 = AHB Bus clock