Rainbow Electronics W90P710CDG - Manual (Page 522)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 523 - Revision B2
7.3.5 LCD Interface AC Characteristics
T
HOLD
T
DELAY
VCLK
VSYNC
HSYNC
VDEN
VD[23:0]
T
PIXCLK
valid data
SYMBOLS DESCRIPTION MIN MAX UNIT
T
PIXCLK
Pixel clock frequency - 40 MHz
T
DELAY
VSYNC, HSYNC, VDEN and VD[23:0] output delay from
VCLK rising edge
5 15 ns
T
HOLD
VSYNC, HSYNC, VDEN and VD[23:0] output data hold
time from VCLK rising edge
0 5 ns