Rainbow Electronics W90P710CDG User Manual
Page 92
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W90P710CD/W90P710CDG
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31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
RESERVED WRBEN
DCAEN
ICAEN
BITS
DESCRIPTION
[31:3] RESERVED
-
[2] WRBEN
Write buffer enable
Write buffer is disabled after reset.
1 = Enable write buffer
0 = Disable write buffer
[1] DCAEN
D-Cache enable
D-Cache is disabled after reset.
1 = Enable D-cache
0 = Disable D-cache
[0] ICAEN
I-Cache enable
I-Cache is disabled after reset.
1 = Enable I-cache
0 = Disable I-cache
Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
y
Flush I-Cache and D-Cache
y
Load and lock I-Cache and D-Cache
y
Unlock I-Cache and D-Cache
y
Drain write buffer
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.