Rainbow Electronics W90P710CDG User Manual

Page 37

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W90P710CD/W90P710CDG

Publication Release Date: September 19, 2006

- 37 -

Revision B2

Table 6.2.1 On-Chip Peripherals Memory Map (Continued)

BASE ADDRESS

DESCRIPTION

APB Peripherals

0xFFF8_7000

Pulse Width Modulation (PWM) Control Registers

0xFFF8_8000

KeyPad Interface Control Register (KPI)

0xFFF8_9000

PS2 Control Registers

6.2.3 Address Bus Generation

The W90P710 address bus generation is depended on the required data bus width of each memory
bank. The data bus width is determined by DBWD bits in each bank’s control register.
The maximum accessible memory size of each external IO bank is 16M bytes.

Table 6.2.2 Address Bus Generation Guidelines

DATA BUS

EXTERNAL ADDRESS PINS

WIDTH A

[21:0]

MAXIMUM ACCESSIBLE MEMORY

SIZE

8-bit

A21 – A0

(Internal)

4M bytes

16-bit

A22 – A1

(Internal)

4M half-words

32-bit

A23 – A2

(Internal)

4M words

6.2.4 Data Bus Connection with External Memory

6.2.4.1 Memory

formats

The W90P710 can be configured as big endian or little endian mode by pull up or down the external data
bus D14 pin. If D14 is pull-up then it is a little endian mode, otherwise, it is a big endian mode.

Little endian

In little endian format, the lowest addressed byte in a word is considered the least significant byte of the
word and the highest addressed byte is the most significant. So the byte at address 0 of the memory
system connects to data lines 7 through 0.
For a word aligned address A, Fig6.2.2 shows how the word at address A, the half-word at addresses A
and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when D14 pin is High.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6 5 4 3 2

1

0

Word at address A

Half-word at address A+2

Half-word at address A

Byte at address A+3

Byte at address A+2

Byte at address A+1

Byte at address A

Fig6.2.2 Little endian addresses of bytes and half-words within words

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