Rainbow Electronics W90P710CDG User Manual
Page 94
W90P710CD/W90P710CDG
- 94 -
NOTE：When using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute
entire I-Cache and D-Cache flushing or unlocking. But, FLHS and ULKS commands can only be
executed with a cache line specified by CAHADR register in I-Cache or D-Cache at a time. If you set
both ICAH and DCAH bits, and set FLHS or ULKS command bit, it will be treated as an invalid
command and no operation is done and the command terminates with no exception.
The Drain Write Buffer operation is only for D-Cache. To perform this operation, you must set DRWB
and DCAH bits. If the ICAH bit is set when using DRWB command, it will be an invalid command and no
operation is done and the command terminates with no exception.
Address Register (CAHADR)
W90P710 Cache Controller supports one address register. This address register is used with the
command set in the control register (CAHCON) by specifying instruction/data address.
REGISTER ADDRESS R/W
DESCRIPTION
RESET
VALUE
CAHADR 0xFFF0_2008 R/W Cache
address register
0x0000_0000
31
30
29
28
27
26
25
24
WAY ADDR
23
22
21
20
19
18
17
16
ADDR
15
14
13
12
11
10
9
8
ADDR
7
6
5
4
3
2
1
0
ADDR
BITS
DESCRIPTION
[31] WAY
Way selection
0 = Way0 is selected
1 = Way1 is selected
[30:0]
ADDR
The absolute address of instruction or data