Rainbow Electronics W90P710CDG - Manual (Page 452)

W90P710CD/W90P710CDG
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Contiuned
BITS DESCRIPTIONS
[5] TBRE
Transmitter Buffer Register Empty
In non-FIFO mode, this bit will be set to a logical 1 when a data
byte is transferred from TBR to TSR. If ETBREI of IER is a logical
1, an interrupt is generated to notify host to write the following data
bytes. In FIFO mode, this bit is set to "1" when the transmitter FIFO
is empty. It is cleared to "0" when host writes data bytes into TBR
or FIFO.
[4] SBD
Silent Byte Detected
This bit is set to "1" to indicate that received data byte are kept in
silent state for a full byte time, including start bit, data bits, parity
bit, and stop bits. In FIFO mode, it indicates the same condition for
the data on top of FIFO. When host reads SCSR, it clears this bit
to "0".
[3] NSER
No Stop bit Error
This bit is set to "1" to indicate that received data has no stop bit.
In FIFO mode, it indicates the same condition for the data on top of
FIFO. When host reads SCSR, it clears this bit to "0".
[2] PBER
Parity Bit Error
This bit is set to "1" to indicate that parity bit of received data is
wrong. In FIFO mode, it indicates the same condition for the data
on top of the FIFO. When host reads SCSR, it clears this bit to "0".
[1] OER
Overrun Error
This bit is set to "1" to indicate previously received data is
overwritten by the next received data before it is read by host. In
FIFO mode, it indicates the same condition instead of FIFO full.
When host reads SCSR, it clears this bit to "0".
[0] RDR
Receiver Data Ready
This bit is set to "1" to indicate received data is ready to be read by
host in RBR or FIFO. If no data are left in RBR or FIFO, the bit is
cleared to "0".
Smart Card Host Guard Time Register (SCHI_GTR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SCHI_GTR0 0xFFF8_5018 R/W Guard time Register 0 0x0000_0001
SCHI_GTR1 0xFFF8_5818 R/W Guard time Register 1 0x0000_0001