Rainbow Electronics W90P710CDG - Manual (Page 48)

W90P710CD/W90P710CDG
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FOUT
(PLL)
HCLK
idle_state
MCLK
(ARM)
HCLK
(cache)
IDLE Period
HCLK
(memc)
Case1. IDLE=1, PD=0, MIDLE=0
Fig. 6.2.7 Clock management for system idle mode
FOUT
(PLL)
HCLK
idle_state
MCLK
(ARM)
HCLK
(cache)
IDLE Period
HCLK
(memc)
Case2. IDLE=1, PD=0, MIDLE=1
Fig. 6.2.8 Clock management for system and memory idle mode
Power Down Mode
This mode provides the minimum power consumption. When the W90P710 system is not working or
waiting an external event, software can write PD bit “1” to turn off all the clocks includes system crystal
oscillator to let ARM CORE enter sleep mode. In this state, all peripherals are also in sleep mode
since the clock source is stopped. W90P710 will exit power down state when nIRQ/nFIQ is detected.
W90P710 provides external interrupt nIRQ[3:0], keypad, and USB device interfaces to wakeup the
system clock.