Rainbow Electronics W90P710CDG - Manual (Page 488)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 489 - Revision B2
USI Data Receive Register 0/1/2/3 (USI_Rx0/1/2/3)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
USI_RX0 0xFFF8_6210 R USI Data Receive Register 0 0x0000_0000
USI_RX1 0xFFF8_6214 R USI Data Receive Register 1 0x0000_0000
USI_RX2 0xFFF8_6218 R USI Data Receive Register 2 0x0000_0000
USI_RX3 0xFFF8_621C R USI Data Receive Register 3 0x0000_0000
31 30 29 28 27 26 25 24
Rx [31:24]
23 22 21 20 19 18 17 16
Rx [23:16]
15 14 13 12 11 10 9 8
Rx [15:8]
7 6 5 4 3 2 1 0
Rx [7:0]
BITS DESCRIPTIONS
[31:0] Rx
Data Receive Register
The Data Receive Registers hold the value of received data of the last
executed transfer. Valid bits depend on the transmit bit length field in the
CNTRL register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and
CNTRL[Tx_NUM] is set to 0x0, bit Rx0[7:0] holds the received data.
NOTE: The Data Receive Registers are read only registers. A Write to
these registers will actually modify the Data Transmit Registers because
those registers share the same FFs.
Data Transmit Register 0/1/2/3 (Tx0/1/2/3)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
USI_TX0 0xFFF8_6210 W USI Data Transmit Register 0 0x0000_0000
USI_TX1 0xFFF8_6214 W USI Data Transmit Register 1 0x0000_0000
USI_TX2 0xFFF8_6218 W USI Data Transmit Register 2 0x0000_0000
USI_TX3 0xFFF8_621C W USI Data Transmit Register 3 0x0000_0000