Standby mode, Extended standby mode, Minimizing power consumption – Rainbow Electronics ATmega32L User Manual
Page 32: Analog to digital converter, Atmega32(l)
32
ATmega32(L)
2503C–AVR–10/02
Asynchronous Timer should be considered undefined after wake-up in Power-save
mode if AS2 is 0.
This sleep mode basically halts all clocks except clk
ASY
, allowing operation only of asyn-
chronous modules, including Timer/Counter2 if clocked asynchronously.
Standby Mode
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,
the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to
Power-down with the exception that the Oscillator is kept running. From Standby mode,
the device wakes up in six clock cycles.
Extended Standby Mode
When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected,
the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is
identical to Power-save mode with the exception that the Oscillator is kept running.
From Extended Standby mode, the device wakes up in six clock cycles..
Notes:
1. External Crystal or resonator selected as clock source.
2. If AS
2
bit in ASSR is set.
3. Only INT2 or level interrupt INT1 and INT0.
Minimizing Power
Consumption
There are several issues to consider when trying to minimize the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as possi-
ble, and the sleep mode should be selected so that as few as possible of the device’s
functions are operating. All functions not needed should be disabled. In particular, the
following modules may need special consideration when trying to achieve the lowest
possible power consumption.
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should
be disabled before entering any sleep mode. When the ADC is turned off and on again,
the next conversion will be an extended conversion. Refer to “Analog to Digital Con-
verter” on page 199 for details on ADC operation.
Table 14. Active Clock Domains and Wake Up Sources in the Different Sleep Modes
Active Clock domains
Oscillators
Wake-up Sources
Sleep Mode
cl
k
CP
U
cl
k
FL
AS
H
cl
k
IO
cl
k
ADC
cl
k
AS
Y
Mai
n
Cl
o
c
k
So
u
rce E
n
ab
le
d
T
imer O
scill
ato
r
En
ab
led
IN
T
2
IN
T
1
IN
T
0
T
W
I A
d
d
ress
Mat
c
h
Ti
m
e
r
2
SP
M / EE
PR
O
M
Read
y
ADC
Ot
he
r
I/
O
Idle
X
X
X
X
X
(2)
X
X
X
X
X
X
ADC Noise
Reduction
X
X
X
X
(2)
X
(3)
X
X
X
X
Power-down
X
(3)
X
Power-save
X
(2)
X
(2)
X
(3)
X
X
(2)
Standby
(1)
X
X
(3)
X
Extended
Standby
(1)
X
(2)
X
X
(2)
X
(3)
X
X
(2)