Rainbow Electronics ATmega32L - Manual (Page 76)

76
ATmega32(L)
2503C–AVR–10/02
Timer/Counter Timing
Diagrams The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when interrupt flags are set. Figure 34 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 34. Timer/Counter Timing Diagram, no Prescaling
Figure 35 shows the same timing data, but with the prescaler enabled.
Figure 35. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 36 shows the setting of OCF0 in all modes except CTC mode.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)