2 power-down, Cs4234 – Cirrus Logic CS4234 User Manual

Page 22

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DS899F1

22

CS4234

4.2.2

Power-down

To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn-
ing off the power. In order to do this in a controlled manner, it is recommended that all the converters be
muted to start the sequence. Next, set PDNx for all converters to 1 to power them down internally. Then,
FS/LRCK and SCLK can be removed if desired. Finally, the

“VQ RAMP” bit in the

"DAC Control 4" register

must be set to ‘1’ for a period of 50 ms before applying reset or removing power or MCLK. During this
time, voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this
50 ms time period has passed, a transient will occur and a slight click or pop may be heard. There is no
minimum time for a power cycle. Power may be reapplied at any time.

It is important to note that all clocks should be applied and removed in the order specified in

Figure 9

. If

MCLK is removed or applied before

RST

has been pulled low, audible pops, clicks and/or distortion can

result. If either SCLK or FS/LRCK is removed or applied before all PDNx bits are set to “1”, audible pops,
clicks and/or distortion can result.

Note: Timings are approximate and based upon the nominal value of the passive components specified in the

“Typical Connection Diagram” on page 8

. See

Section 4.6.6.2

for volume ramp behavior.

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