Cirrus Logic CS4234 - Manual (Page 4)

DS899F1 4
CS4234
6.25 Interrupt Notification 2 (Address 22h) (Read Only) ...................................................................... 69
7. ADC FILTER PLOTS ............................................................................................................................ 70
8. DAC FILTER PLOTS ............................................................................................................................ 71
9. PACKAGE DIMENSIONS ................................................................................................................... 73
10. ORDERING INFORMATION .............................................................................................................. 74
11. APPENDIX A:INTERNAL TRACKING POWER SUPPLY SIGNAL .................................................. 74
11.1 Voltage Headroom ....................................................................................................................... 76
11.2 Lead Time .................................................................................................................................... 76
11.3 Gain Matching .............................................................................................................................. 76
11.4 SMPS (TPS) Modes ..................................................................................................................... 77
12. REVISION HISTORY .......................................................................................................................... 79
LIST OF FIGURES
Figure 1. CS4234 Pinout ............................................................................................................................. 6
Figure 2. Typical Connection Diagram ........................................................................................................ 8
Figure 3. Test Circuit for ADC Performance Testing ................................................................................. 13
Figure 4. PSRR Test Configuration ........................................................................................................... 13
Figure 5. Equivalent Output Test Load ..................................................................................................... 15
Figure 6. TDM Serial Audio Interface Timing ............................................................................................ 19
Figure 7. PCM Serial Audio Interface Timing ............................................................................................ 19
Figure 8. I²C Control Port Timing .............................................................................................................. 20
Figure 9. System Level Initialization and Power-up / Power-down Sequence .......................................... 23
Figure 10. DAC DC Loading ..................................................................................................................... 24
Figure 11. Timing, I²C Write ...................................................................................................................... 25
Figure 12. Timing, I²C Read ...................................................................................................................... 25
Figure 13. Master Mode Clocking ............................................................................................................. 27
Figure 14. TDM System Clock Format ...................................................................................................... 28
Figure 15. 32-bit Receiver Channel Block ................................................................................................. 29
Figure 16. Serial Data Coding and Extraction Options within the TDM Streams ...................................... 30
Figure 17. Left Justified Format ................................................................................................................ 31
Figure 18. I²S Format ................................................................................................................................ 31
Figure 19. Audio Path Routing .................................................................................................................. 32
Figure 20. Conventional SDOUT1 (Left) vs. Sidechain SDOUT1 (Right) Configuration ........................... 33
Figure 21. DAC1-4, Low Latency, and DAC5 Path Serial Data Source Selection .................................... 34
Figure 22. Example Serial Data Source Selection .................................................................................... 35
Figure 23. ADC Path ................................................................................................................................. 38
Figure 24. DAC1-4 Path ............................................................................................................................ 39
Figure 25. De-emphasis Curve ................................................................................................................. 40
Figure 26. Low-latency Path ..................................................................................................................... 40
Figure 27. DAC5 Path ............................................................................................................................... 41
Figure 28. Volume Implementation for the DAC1-4 and Low-latency Path ............................................... 43
Figure 29. Volume Implementation for the DAC5 Path ............................................................................. 43
Figure 30. Soft Ramp Behavior ................................................................................................................. 45
Figure 31. Interrupt Behavior and Example Interrupt Service Routine ...................................................... 49
Figure 32. ADC Stopband Rejection ......................................................................................................... 70
Figure 33. ADC Transition Band ............................................................................................................... 70
Figure 34. ADC Transition Band (Detail) ................................................................................................... 70
Figure 35. ADC Passband Ripple ............................................................................................................. 70
Figure 36. ADC HPF (48 kHz) ................................................................................................................... 70
Figure 37. ADC HPF (96 kHz) ................................................................................................................... 70
Figure 38. SSM DAC Stopband Rejection ................................................................................................ 71
Figure 39. SSM DAC Transition Band ...................................................................................................... 71
Figure 40. SSM DAC Transition Band (Detail) .......................................................................................... 71