Figure 15. 32-bit receiver channel block, Figure 15, Data is clocked out of – Cirrus Logic CS4234 User Manual
Page 29: Cs4234
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DS899F1
29
CS4234
The structure in which the serial data is coded into the TDM slots is shown in
. When using a
48 kHz sample rate with a 24.576 MHz MCLK and SCLK, a 16 slot TDM structure can be realized. When
using a 48 kHz sample rate with 12.288 MHz SCLK and 24.576 MHz MCLK, or a 96 kHz sample rate with
a 24.576 MHz MCLK and SCLK, an 8 slot TDM structure can be realized. The data that is coded into the
TDM slots is extracted into the appropriate signal path via the settings in the Control port. Please refer to
Section 4.6.1 Routing the Serial Data within the Signal Paths
for more details.
MSB
32-Bit Channel Block
LSB
24-Bit Audio Word
8-Bit Zero Pad
(Or DAC5 Data)
-1
-2
-3
-4
-5
-6
-7
+1
+2
+3
Figure 15. 32-bit Receiver Channel Block
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