3 clock and sp select (address 06h), 1 base rate advisory, 2 speed mode – Cirrus Logic CS4234 User Manual
Page 53: 3 master clock rate, Master clock rate, Speed mode, Bits con, Base rate advisory” bits in the, Clock and sp select (address 06h)" register, Base rate advisory
DS899F1
53
CS4234
6.3
Clock and SP Select (Address 06h)
6.3.1
Base Rate Advisory
Advises the CS4234 of the base rate of the incoming base rate. This allows for the de-emphasis filters to
be adjusted appropriately and the group delay block for the DAC1-4 path to be calculated correctly. The
CS4234 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz base rates. It is not supported for
96 kHz or for any settings in Double Speed Mode.
6.3.2
Speed Mode
Sets the speed mode in which the CS4234 will operate.
6.3.3
Master Clock Rate
Sets the rate at which the master clock is entering the CS4234. Settings are given in “x” multiplied by the
incoming sample rate, as MCLK must scale directly with incoming sample rate.
7
6
5
4
3
2
1
0
BASE RATE[1:0]
SPEED MODE[1:0]
MCLK RATE[2:0]
Reserved
BASE RATE
Base Rate is:
00
48 kHz
01
44.1 kHz
10
32 kHz
11
Reserved
SPEED MODE
Speed Mode is:
00
Single Speed Mode
01
Double Speed Mode
10
Reserved
11
Auto Detect
MCLK RATE
MCLK is:
000
256xF
S
in Single Speed Mode or 128xF
S
in Double Speed Mode
001
384xF
S
in Single Speed Mode or 192xF
S
in Double Speed Mode
010
512xF
S
in Single Speed Mode or 256xF
S
in Double Speed Modex
011
Reserved
100
Reserved
101
Reserved
110
Reserved
111
Reserved