4 low-latency path, Figure 25, Cs4234 – Cirrus Logic CS4234 User Manual

Page 40: Figure 26. low-latency path, 10db, Figure 25. de-emphasis curve

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DS899F1

40

CS4234

The de-emphasis feature is included to accommodate audio recordings that utilize 50/15

s preemphasis

equalization as a means of noise reduction.

De-emphasis is only available in Single-speed Mode.

4.6.4

Low-Latency Path

A low-latency path is provided to allow four user selectable data signals to be routed around the group
delay block and interpolation filters of the DAC1-4 path. These four signals can be present in any of the
32 slots on the two TDM streams on SDIN1 and SDIN2.

The Low-Latency path also includes a global mute bit and individual channel invert bits. The signals from
the low latency path are summed with the DAC1-4 path after the master volume control. Changes to the
master volume control setting do not affect the low-latency-path signals. For details concerning the oper-
ation of the volume control, please see

Section 4.6.6 Volume Control

.

Gain

dB

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1

F2

3.183 kHz

10.61 kHz

Figure 25. De-emphasis Curve

Gain / Volume

AIN4 (±)

AIN3 (±)

AIN2 (±)

AIN1 (±)

Interpolation

Filter

Channel Volume ,

Mute, Invert,

Noise Gate

Multi-bit



Modulators

AOUT1 (±)
AOUT2 (±)
AOUT3 (±)
AOUT4 (±)

I

2

C Control

Data

Control Port

Level Translator

VL

1.8 to 5.0 VDC

RST

INT

SDIN1

SDOUTx

Group

Delay

0-500uS

Master Clock In

Frame Sync

Clock / LRCK

SDIN 2

Serial Clock

In / Out

LDO

Analog Supply

2.5 V

VA

5.0 VDC

VD

2.5 VDC

Low -Latency

Demux

5

th

DAC

Input Advisory

DAC &
Analog

Filters

Tracking

SMPS

Enable

Sample

& Hold

Mute, Invert,

Noise Gate

Master

Volume
Control

Serial Audio Interface

AOUT 5 (±)

(SMPS Control )

DAC &
Analog

Filters

Master

Vol . Cntrl

Select

Master Volume

0 dB

TPS

GAIN

Filter

Select

X

Interpolation Filter

Sample & Hold

Max

Detect

Envelope

Tracking

Mute, Invert,

Noise Gate

DAC

Volume

Multi-bit



Modulators

Mode

Select

Full Scale Code

X

DC Offset

Digital Filters

Multi-bit

 ADC

-2

X

Gain

S elect

-1

Figure 26. Low-latency Path

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